1. Field of the Invention
The present invention relates to a semiconductor apparatus having a trench-gate structure and a method of manufacturing the same.
2. Description of Related Art
As an example of a semiconductor apparatus having a trench-gate structure according to a related art, a vertical power MOSFET is shown in FIG. 6. FIG. 6 is a vertical sectional view of a vertical power MOSFET 10 according to a related art.
Referring to FIG. 6, the vertical power MOSFET 10 includes an n+ layer 20, an n− layer 30, a body p layer 40, a p+ layer 50, source layers 60a and 60b, gate insulating films 70a and 70b, gate electrode layers 80a and 80b, cap oxide layers 90a and 90b as cap insulating layers, trenches 100a and 100b, a source electrode 110, and a drain electrode 120.
In the vertical power MOSFET 10, the body p layer 40 is formed above the n+ layer 20 and the n− layer 30, which serve as a drain. Further, the p+ layer 50 is formed on the surface of the body p layer 40.
The gate insulating films 70a and 70b are formed on the inner wall surfaces of the trenches 100a and 100b that are formed in prescribed positions. The gate electrode layers 80a and 80b, which are made of a polysilicon film, are formed inside the trenches. The top surfaces of the gate electrode layers 80a and 80b are covered with the cap oxide layers 90a and 90b. 
In order to reduce the resistance (gate resistance) of the gate electrode layers 80a and 80b, a relatively high concentration of n-type impurity (e.g. phosphorus: P) is doped to the polysilicon film that fills the inside of each trench.
Consequently, the cap oxide layers 90a and 90b, which are formed by thermally oxidizing the surface of the doped polysilicon film, also contain a high concentration of n-type impurity (e.g. phosphorus: P).
On the surface of the body p layer 40, the source layers 60a and 60b are formed in contact with the gate insulating films 70a and 70b. The part of the body p layer 40 which is in contact with the gate insulating films 70a and 70b serves as a channel region.
On the front surface of the substrate, the source electrode 110 is formed in contact with the p+ layer 50 and the source layers 60a and 60b. The drain electrode 120 is formed on the rear surface of the substrate.
In the vertical power MOSFET 10 having such a structure, the gate electrode layers 80a and 80b are electrically isolated from the source electrode 110 by the cap oxide layers 90a and 90b. Further, because this structure establishes source contact on the substrate surface without forming a trench for establishing source contact, it is suitable for cell shrinkage.
A method of manufacturing the vertical power MOSFET 10 having such a structure is described hereinafter with reference to FIGS. 7A to 7C and 8D to 8F. FIGS. 7A to 7C and 8D to 8F are sectional views showing the substantial part of the manufacturing process at each completion of fundamental steps. In FIGS. 7A to 7C and 8D to 8F, the n+ layer 20 shown in FIG. 6 is not illustrated.
Referring first to FIG. 7A, a trench mask 150, which is made of a silicon nitride film (Si3N4), is formed above the n− layer 30 (drain) and the body p (p−) layer 40. Then, arsenic (As) is implanted as shown in the dotted line in FIG. 7A in order to form a source layer. Then, side walls 160a and 160b are formed on both sides of the trench mask 150.
The side walls 160a and 160b are formed by depositing a SiO2 film all over the substrate using a CVD process and then performing RIE (Reactive Ion Etching) to remove the SiO2 film on the trench mask 150.
Referring next to FIG. 7B, the substrate is etched by RIE using the trench mask 150 and the side walls 160a and 160b as masks, thereby forming the trenches 100a and 100b. 
In this step, a part of the implanted arsenic (As) remains under the side walls 160a and 160b without being removed.
Referring then to FIG. 7C, damage of the substrate, which is caused by the formation of the trenches, is recovered by performing sacrifice-oxidation and removing a sacrifice oxide film (not shown).
Due to heat treatment during the sacrifice-oxidation, a part of the remaining arsenic (As) is activated; as a result, first portions 61a and 61b, which are components of a ladder-like source layer, are formed.
After that, the inner wall surfaces of the trenches 100a and 100b are oxidized by heat treatment to thereby form the gate insulating films 70a and 70b. Due to the heat treatment, the first portions 61a and 61b of the source layer expand outward.
Referring further to FIG. 8D, each trench is filled with a polysilicon 80 that is doped with an n-type impurity (e.g. phosphorus: P) in order to reduce gate resistance.
Specifically, the polysilicon film 80 is deposited inside the trenches 100a and 100b and on the substrate surface by the CVD process, and then an unnecessary part is removed (etched back) by RIE.
Referring then to FIG. 8E, the surface of the doped polysilicon film that is filled inside the trenches 100a and 100b is thermally oxidized using the trench mask 150 as a mask to thereby form the cap oxide layers 90a and 90b. After that, the trench mask 150 is removed.
A non-oxidized part of the doped polysilicon film that is filled inside the trenches 100a and 100b thereby becomes the gate electrode layers 80a and 80b. 
Because the cap oxide layers 90a and 90b cubically expand as the oxidation progresses, the top surfaces of the cap oxide layers 90a and 90b become higher than the top surface of the substrate. On the other hand, the under surfaces of the cap oxide layers 90a and 90b become lower than the top surface of the substrate. Accordingly, the thickness of the gate electrode layers 80a and 80b decreases.
Referring finally to FIG. 8F, a resist mask (not shown) having a prescribed pattern (an opening pattern that is equivalent to a second portion corresponding to a crossbar of the ladder-like source layer) is formed orthogonal to the trenches 100a and 100b, and arsenic (As) is implanted onto the substrate surface. Then, the implanted arsenic (As) is activated by heat treatment to thereby form a second portion 62, which is a component of the ladder-like source layer.
After that, side walls (not shown) to cover the first portions 61a and 61b are formed on both sides of the cap oxide layers 90a and 90b. Then, a p-type impurity (e.g. boron: B) is implanted onto the surface of the body p layer 40, and annealing is performed to thereby form the p+ layer 50. Because the concentration of the n-type impurity of the second portion 62 is higher than the concentration of the implanted p-type impurity, there arises no problem.
Then, the side walls (not shown) are removed, and the source electrode 110 and the drain electrode 120 are formed on the front surface and the rear surface of the substrate, respectively. The vertical power MOSFET 10 is thereby completed. Such a vertical power MOSFET is disclosed in Japanese Patent No. 3489358, for example.
In the above vertical power MOSFET 10, the gate electrode layers 80a and 80b are formed by filling the trenches with a doped polysilicon that contains a relatively high concentration of impurity in order to reduce gate resistance. Consequently, the cap oxide layers 90a and 90b, which are formed by thermally oxidizing the surface of the doped polysilicon, also contain a high concentration of impurity.
If the cap oxide layers 90a and 90b contain such a high concentration of impurity, the high-concentration impurity diffuses from the substrate surface during the heat treatment and reaches a channel region through the source layers 60a and 60b, which can cause short-circuit between a source and a drain.
Further, when forming the cap oxide layers 90a and 90b by thermally oxidizing the surface of the doped polysilicon, the cap oxide layers 90a and 90b expand as the thermal oxidation progresses. Consequently, the positions of the under surfaces of the cap oxide layer 90a and 90b become lower, so that the thickness of the gate electrode layers 80a and 80b changes (decreases) accordingly. It is thus difficult to stably obtain a prescribed thickness of the gate electrode layers 80a and 80b. 
Furthermore, if the thermal oxidation progresses excessively and the under surfaces of the cap oxide layer 90a and 90b become lower than the source layers 60a and 60b, it hampers the formation of a normal channel.